1. Field of the Invention
This invention relates to semiconductor devices and more particularly to shallow trench isolation in self-aligned FET devices.
2. Description of Related Art
Conventional STI (Shallow Trench Isolation) planarization methods require a planarization mask, extensive measurements, and wafer-to-wafer process customization.
Maskless STI Planarization using Self-Aligned Polysilicon process allows STI to be planarized without a planarization mask, with minimal measurements and no need for wafer to wafer customization and can be designed to be completely ground rule compatible with a gate conductor stack Fill technology.
U.S. Pat. No. 5,173,439 of Dash et al. for "Forming Wide Dielectric-Filled Isolation Trenches In Semi-conductors" shows isolation trenches formed in pad silicon nitride/Si, followed by a silicon oxide layer, followed by a polysilicon layer, followed by Chemical Mechanical Polishing (CMP); followed by silicon oxide RIE (Reactive Ion Etching); followed by CMP down to a pad silicon nitride layer.
U.S. Pat. No. 5,504,033 of Bajor et al. for "Method for Forming Recessed Oxide Isolation Containing Deep And Shallow Trenches" describes in a fifth embodiment, after isolation trenches are dug into silicon nitride over silicon oxide over silicon, the trenches along with horizontal surfaces are first layered with silicon oxide, then sequentially a polysilicon layer; is followed by CMP. This reference appears not to address selective RIE partial silicon oxide etch over pad areas.
U.S. Pat. No. 5,411,913 of Bashir et al. for "Simple Planarized Trench Isolation and Field Oxide Formation using Poly-silicon" where after trenches are dug into pad silicon oxide/silicon nitride and into silicon; a layer of silicon oxide is deposited, followed by a layer of polysilicon, followed by RIE etch back to planarize. This reference appears not to address CMP polishing down to the silicon oxide layer and selective RIE partial silicon oxide etching over pad areas.
U.S. Pat. No. 5,492,858 of Bose et al. for "Shallow Trench Isolation Process Method for High Aspect Ratio Trenches" in which, after isolation trenches are dug through the pad silicon oxide/silicon nitride into silicon, a layer of silicon oxide is deposited and CMP etched back to silicon nitride to provide a planar surface for "active mesa sites." Bose et al. does not address deposition of polysilicon on a silicon oxide layer; CMP polishing down to the silicon oxide layer; and selective RIE partial silicon oxide etching over pad areas.
U.S. Pat. No. 5,494,857 of Cooperman et al. for "Chemical Mechanical Planarization of Shallow Trenches in Semiconductor Substrates" where, after trenches are dug in through pad silicon nitride/silicon oxide, a first silicon oxide layer is deposited, followed by a first silicon etch stop layer, followed by a second silicon oxide layer; followed by a CMP down to pad silicon nitride.
U.S. Pat. No. 5,252,517 of Blalock et al. for "Method Of Conductor Isolation From A Conductive Contact Plug", where, after transistors are completed, a "planarizing insulator layer" is deposited and contact vias are etched down to diffusion areas and filled with polysilicon.
U.S. Pat. No. 5,358,884 of Violette for "Dual Purpose Contact Collector Contact and Isolation Scheme for Advanced BICMOS Processes" shows trenches are dug through silicon nitride into silicon. Silicon oxide is deposited upon the silicon nitride, and CMP is done down to silicon nitride to create a "plurality of mesas."
FIG. 3 shows an isolation region of a prior art MOSFET device 60 with a doped silicon semiconductor substrate 62 on which an STI region 72 has been formed. Above the STI region is formed a gate conductor stack 74 of fill layers comprising a polysilicon layer 64, a silicide layer 68, and a silicon nitride gate insulator layer 70.
See J.-Y. Cheng, T. F. Lei, T. S. Chao, D. L. W. Yen, B. J. Jin, and C. J. Lin "A Novel Planarization of Oxide-Filled Shallow-Trench Isolation" J. Electrochem. Soc., Vol. 144, No.1, (January, 1997) pp. 315-320.